1. Express the floating-point number -7.3125 in single precision IEEE floating-point format. Write your answer in hexadecimal. You must show your work for credit.

    answer: c0ea0000

  2. If a multiplexor has n inputs how many selector wires does it require?

    answer: log2(n)

  3. If n bits of an address are used to specify a block in a direct mapped cache how many blocks does the cache have?

    answer: 2n

  4. If a set associative cache has n sets how many bits are needed in the address to specify the set the address maps to?

    answer: log2(n)

  5. Why does the MIPS need exactly five bits to specify the destination register in an R-type instruction?

    answer: log2(32)

  6. What is log2(2n)

    answer: n

  7. If a decoder has n inputs, how many outputs does it have?

    answer: log2(n)

  8. What is a page table?

    answer: A table that associates pages to frames.

  9. Assume we have 32 bit addresses and a page size of 8K bytes. Mow many entries can the page table contain?

    answer: 232 ÷ 213 = 219 (or 512K)

  10. What floating-point number does 0xC2078000 represent when interpreted as a sinlge precision IEEE floating-point number? Express your answer in decimal. You must show work to receive credit.

    answer: -33.875

  11. What is temporal locality?

    answer: see book/notes

  12. What is spatial locality?

    answer: see book/notes

  13. What is a page fault?

    answer: see book/notes

  14. Is the cycle time of the pipelined MIPS more or less than the cycle time of the single cycle MIPS? Explain your answer in one sentence.

    Less because an instruction completes over five short cycles as opposed to one longer single cycle

  15. Name three problems virtual memory solves.

    answer: Here are more than three. 1) code sharing between programs, 2) fragmentation, 3) programmer/assembler/compiler use logical addresses as opposed to physical address giving the program the illusion that it has the entire address space to itself, 4) have more logical memory than physical memory 5) saves memory as unused portions of program get swapped out

  16. Are memory accesses in a system with virtual memory faster or slower than in a system without virtual memory? Briefly explain your answer. Describe one technique used to address performance problems in virtual memory.

    answer: slower because every memory access requires an additional memory access to the page table

  17. Consider the single cycle MIPS datapath on page 322 of the book. What instruction(s) would be broken if the MemToReg control line between the control unit and the Mux was stuck-at-0?

    answer: lw would be broken because we could never get data out of memory.

  18. Suppose a program has a miss rate of 6% for data accesses and 4% for instruction accesses; a miss penalty of 40 cycles; the frequency of lw/sw instructions is 35%; a CPI of 2 if the cache's hit ratio was 100%. What is the speedup for this program with a system that has a cache over a system that has no caches at all?
    1. Speedup = CPInocache÷ CPIwithcache
    2. CPInocache = 2 + MissCPI where the miss rate is 100%
    3. MissCPInocache = (DataMissCyclesnocache + InstMissCyclesnocache)/IC
    4. DataMissCyclesnocache = (IC)(0.35)(40)(miss rate)
    5. InstMissCyclesnocache = (IC)(40)(miss rate)
    6. MissCPInocache=(54)IC
    7. CPInocache = 56
    8. CPIwithcache = 2 + MissCPI where miss rates are from question descriptions
    9. MissCPIwithcache = (DataMissCycleswithcache + InstMissCycleswithcache)/IC
    10. DataMissCycleswithcache = (IC)(0.35)(40)(.06)
    11. InstMissCycleswithcache = (IC)(40)(.04)
    12. MissCPIwithcache=(2.44)IC
    13. CPIwithcache = 4.44
    14. Speedup = 56/4.44 = 12.61
  19. Consider the following MIPS code fragment 
    lw $t3, 0($t0)    ; instruction 1
add $t3, $t3, $t3 ; instruction 2
sw $t3, 0($t0)    ; instruction 3
    1. List all of the dependencies above by describing where the depenencies occur, on which registers, and the kind of dependency.

      answer:2 depends on 1, 3 depends on 1, 3 depends on 2

    2. Which dependencies result in a stall in the five stage MIPS pipeline that has EXE forwarding.

      answer: only the dependency between 1 and 2 requires a stall the others are taken care of by forwarding.

  20. Consider a direct mapped cache with 2K blocks, four words per block, and 32-bit addresses. Also assume that addresses must be on a word boundary and that a word is four-bytes.
    1. Show how the bits in an address determine which word in the cache the address maps to.
      1. bits 0-1 in the address are always zero
      2. bits 2-3 in the address specify the offset in the cache block
      3. bits 4-14 specify the block in the cache
      4. bits 15-31 specify the tag
    2. Which block and word in the block does the address 0x0F0FB004 map to?
      1. Writing out the 32 bits we have 
        00001111000011111 10000000000 01 00
      2. So the word in the block is 1
      3. And the block is 1024
    3. What is the size of the cache in the total number of bits?
      1. Each block in the cache contains a valid bit (1 bit), a tag (17 bits), and four words (each word is 32 bits) for a total of 1+17+32(4)=146 bits per block
      2. There are 211 blocks so there are 211(146)=299,008 bits in the cache